A complex electronic circuit (e.g., a Very-Large-Scale-Integration (VLSI) circuit) may include several elements and interconnectors thereof. During gate-level simulation/verification of the electronic circuit, connectivity descriptors (e.g., netlists) of the electronic circuit may be pruned based on a list of regular expressions related to text-matching strings with elements of the electronic circuit. The aforementioned list may be manually provided by a user (e.g., a verification engineer) of a computing device executing the simulation/verification. Due to the manual nature of the aforementioned list-provision process, it may be impossible to scan the complete design of the electronic circuit. Further, the failures of the simulation/verification process may be followed by several iterations for successful completion thereof.
The complexity of the electronic circuit, the impossibility of preconditioning and/or the manual nature of the list-provision process may also combine to leave a large memory footprint during the design simulation/verification. This, combined with the long simulation/verification time, may lead to frustration on part of the verification engineer.